Polished Silicon Wafers
Specifications
Manufacturing Process
Wafer Works' polished silicon wafers consist of 4" - 8" low defect,  superior flatness silicon wafers, containing dopants such as boron, phosphorus, arsenic, and antimony to meet the specific customer requirements. Wafer Works is also conforming to energy-saving trends by providing ultra-high doped silicon wafer, to satisfy low resistance (RDS(on)) inquiry, which is an important factor in low voltage Power MOSFET device.

Specifications of Silicon Substrate

Type Dopant Diameter
(mm)
Resistivity Range
  (ohm.cm)
P Boron 100/125/150/200 0.0006~200
N Phosphorus 100/125/150/200 0.0011~60
N Arsenic 100/125/150/200 0.0020~0.01
N Antimony 100/125/150/200 0.0088~0.03
 
01

Crystal Growth

We use the Czochralski (CZ) method to grow both p-type and n-type dislocation-free silicon ingots with <100>, <111> or <110> orientation. The diameters of the ingots are 100mm, 125mm, 150mm, and 200mm. The dopant types used, and the matching resistivity ranges for each dopant are listed in the product tables. For the p-type boron doped ingots, the lowest resistivity that can be obtained for an ingot is 0.0006 ohm.cm. For an n-type ingot, the lowest resistivity that can be obtained by doping with red-phosphorus is 0.0011 ohm.cm. To ensure high gettering ability and mechanical strength, the oxygen contents of the ingots are regulated. We also pay special attention to improve radial uniformity and to minimize the as-grown defects, such as COP, swirl and dislocation loops in an ingot.  

02

Slicing

Slicing follows the process of cutting the ingot into thin wafer slices. Wafer Works used cutting-edge wire and I.D. saws that are operated by experienced and well-trained operators to produce high quality wafers. The techniques to achieve thin wafers with low kerf loss are applied, which help to ensure wafer flatness and total thickness variation (TTV) is controlled to minimum.
03

Edge Grinding

After slicing process, Wafer Works used edge grinding technology to create rounded edges on each wafer. The purpose of this step is to minimize edge chipping, breakage and thermal induced slip in the subsequent customer's thermal processes. Based on different Epi thickness and/or processes, an optimized edge profile and length can be made with specific customer specifications.

04

Lapping

Lapping is the process where residual slicing damage on the wafer's surface has removed. Initial refinement on wafer flatness is also conducted during this process.
05

Etching

Both acid and caustic etching are available according to customer's requirements. The damaged layers caused by the previous processes are removed during etching process. We can also provide a residual damage layer during the caustic etching process for backside gettering purposes. Special shape control can be achieved with state-of-the-art etching machines and techniques.
06

Backside Treatment

To satisfy customer detailed requirements, Wafer Works is capable of adding LTO, poly-back, or backside damage (BSD) to the backside of wafers. These treatments help to ensure high device yield. For thick poly-back, Wafer Works has developed a unique patented process to ensure wafer flatness.
07

Polishing

Polishing techniques have a big impact on the outcome of the wafer's surface, which is why Wafer Works uses sophisticated polished and a rigorous inspection process to produce world-class silicon wafers. Wafer Works is able to perform tight roughness wafer surface.
08

Cleaning

The cleaning process removes surface metals as well as micro particles away from wafer surface. Wafer Works' engineering group has conducted various experiments that help to modify our cleaning process to perfection stage.
09

Visual Inspection

In order to supply defect-free products to our customers, we have conducted visual inspection on each wafer in the drak room with the assistance of the auxiliary light sources.
10

Wafer Characterization

After the wafer has undergone polishing and cleaning procedures, we use advanced equipment and cutting-edge technology to accurately measure the wafer's resistivity, thickness, TTV, STIR, bow and warp, etc. according to customer's requirements.
11

Wafer Clearance Inspection

To ensure we are delivering high quality wafers to customers, we use precise, state-of-the-art machines that accurately measure particle count on the wafer's surface before packaging.
12

Package

The wafers are desiccated with a nitrogen purge to evacuate humidity down, tape sealed, double bagged (PE + Aluminum Bag), and then vacuum packed in a class 10 clean room environment.